This invention relates to a jitter detecting circuit for detecting jitter contained in a clock signal generated by an oscillating circuit and, more particularly, to a jitter detecting circuit for detecting cycle-to-cycle jitter.
A clock signal gives appropriate timings to a digital circuit. An oscillating circuit is a source of the clock signal, and is usually incorporated in the digital circuit. A phase-locked loop is popular to the skilled person as the source of clock signal. The amount of jitter relates to the stability of the phaselocked loop. It is necessary to detect the jitter generated in the phase-locked loop.
A typical example of the jitter detecting circuit is shown in FIG. 1 of the drawings. The prior art jitter detecting circuit 10a is designed to detect the phase difference between a target signal and a clock signal. The prior art jitter detecting circuit 10a comprises a delay circuit 31a and a flip-flop circuit 32a. The target signal is supplied to the delay circuit 31a, and a delay time is introduced into the propagation of the target signal by the delay circuit, and the delayed target signal and the clock signal are supplied to the two input nodes of the flip-flop circuit 32a. The flip-flop circuit 32a detects the phase difference occurring between the target signal and the clock signal, and produces an output signal representative of the jitter. Two prior art jitter detecting circuits 10a are prepared, and the target signal and the clock signal are alternately supplied thereto. Otherwise, the delay circuits 31a incorporated in plural prior art jitter detecting circuits are arranged in such a manner as to introduce delay times different from one another, and the amount of jitter is determined on the basis of the output signals of the flip-flop circuits 32a. 
Another prior art jitter detecting circuit is disclosed in Japanese Patent Publication No. 7-50926. The prior art jitter detecting circuit is used for a video signal reproduced from an information storage medium. The prior art jitter detecting circuit is associated with an extracting circuit for extracting a horizontal synchronous signal from the video signal, and includes a voltage-controlled oscillating circuit, a frequency demultiplier, a variable ramp voltage generating circuit and a sample-and-hold circuit. The voltage-controlled oscillating circuit oscillates at a frequency n times larger than that of the extracting circuit, and producing an output oscillating signal. The frequency demultiplier reduces the oscillation frequency to 1/n. The variable ramp voltage generating circuit generates the ramp voltage signal varied together with the phase of the output pulse signal of the frequency demultiplier. A sampling pulse signal is produced from the horizontal synchronous signal, and is representative of the horizontal scanning period. The ramp voltage signal is sampled with the sampling pulse signal so as to obtain discrete voltage values. A control signal is produced from the discrete values, and is supplied to the control terminal of the voltage-controlled oscillating circuit and the variable ramp voltage generating circuit. The output oscillating signal serves as a jitter detecting signal.
The following problems are encountered in the prior art jitter detecting circuits. Skilled person notices the clock signal for digital circuits containing a kind of jitter shown in FIG. 2. The jitter shown in FIG. 2 is called as xe2x80x9ccycle-to-cycle jitterxe2x80x9d. The cycle-to-cycle jitter is representative of an off-set between the timings of the continuous clock cycles or variation of relative values of the continuous clock cycles. Since digital circuits are getting faster, the clock signal is expected to be stable, and the clock cycles of the clock signal are to be constant. Not only periodic jitter (see FIG. 3) but also cycle-to-cycle jitter are required for the stable clock signal. The periodic jitter represents the dispersion of absolute values of the clock period.
The prior art jitter detecting circuit 10a shown in FIG. 1 detects the degree of phase difference at points of measurement, and an analyst decides the absolute value of the phase difference between the target signal and the clock signal at points of measurement. In other words, the analyst only decides the periodic jitter shown in FIG. 3. However, the variation of the phase difference is not left in the prior art jitter detecting circuit 10a. For this reason, it is impossible to decide the degree of the cycle-to-cycle jitter by using the prior art jitter detecting circuit 10a. 
As described hereinbefore for the prior art jitter detecting circuit disclosed in the Japanese Patent Publication, the sample-and-hold circuit samples the ramp voltage produced in dependence on the phase of the output pulse signal of the frequency demultiplier with the sampling pulse signal representative of a horizontal scanning period of the horizontal synchronous signal produced in the extracting circuit, and holds the discrete values so as to produce the control signal supplied to the voltage-controlled oscillating circuit. The prior art jitter detecting circuit disclosed in the Japanese Patent Publication can not detect the cycle-to-cycle jitter.
It is therefore an important object of the present invention to provide a jitter detecting circuit, which detects the cycle-to-cycle jitter contained in a target signal.
To accomplish the object, the present invention proposes to store the phase difference in the previous clock cycle so as to compare the phase difference in the previous clock cycle with the phase difference in the current clock cycle. In accordance with one aspect of the present invention, there is provided a jitter detecting circuit for detecting a cycle-to-cycle jitter in a target clock signal comprising at least one jitter detector, and the at least one jitter detector includes a phase difference detecting unit comparing the target clock signal with a reference clock signal to see whether or not a phase difference takes place in a certain clock cycle and changing a first output signal between a first logic level representative of a presence of the phase difference and a second logic level representative of an absence of the phase difference and a state change detecting unit storing a logic level of the first output signal in a previous clock cycle, comparing the logic level of the first output signal in the certain clock cycle with the logic level of the first output signal in the previous clock cycle to see whether or not the first output signal changes the logic level between the previous clock cycle and the certain clock cycle and producing a second output signal representative of the cycle-to-cycle jitter when the phase difference detecting unit changes the first output signal between the first logic level and the second logic level.